1. Field of the Invention
This invention relates in general to the field of memory management within a computing system, and more particularly to an apparatus and method for extending the properties of virtual memory pages above and beyond those provided for by an existing translation lookaside buffer architecture.
2. Description of the Related Art
Early computing systems executed application programs that were composed especially to run on those systems. The programs consisted of a sequence of instructions that were loaded into the memory of the computing system at the time of execution. Address logic within the computing system would generate a memory address each time an instruction was fetched from the memory for execution. Access logic within the computing system would place the memory address out on a memory address bus and the memory would provide the contents of the memory location corresponding to the memory address for execution by the computing system. In addition to program instructions, the early computing systems employed memory locations to temporarily store data that was used by application programs. And like the retrieval of program instructions for execution, the storage and retrieval of program data involved the generation of memory addresses that corresponded to data memory locations.
The memory addresses generated by the address logic were directly routed to the early computing systems"" memory busses to access corresponding memory locations. Hence, to access location 10513BC7h in memory required that the address logic generate address 10513BC7h and issue this address to the memory bus. But stated differently, it also is true that when the address logic generated address 10513BC7h, the memory location to which this address corresponded was also location 10513BC7h.
It is intuitive to observe that a direct, one-to-one correspondence between memory addresses generated by a program executing on an early computing system and locations in the computing system""s memory was quickly deemed disadvantageous from many standpoints. First, in order to execute a wide variety of application programs, it was required that the early computing system always provide memory that spanned the full address range of the system. Second, such correspondence unnecessarily coupled the architecture of the computing system to the tools that were used to produce and execute programs on the system. For instance, programs required modifications in order to execute on computing systems that exhibited different memory ranges and constraints. And finally, as computers progressed to the point of providing time-share (i.e., multi-tasking) operating systems, performance degradations were observed since all memory management and protection functions had to be performed by the operating systems.
Virtual memory techniques were developed during the mid-1970""s specifically to address the above-noted problems. Stated briefly, a virtual memory xe2x80x9cmanagerxe2x80x9d within a computing processing unit (CPU) served as an intermediary between address generation logic in the CPU and access logic that accessed memory locations. Under a virtual memory management scheme, a xe2x80x9cvirtual addressxe2x80x9d generated by the address logic was xe2x80x9ctranslatedxe2x80x9d according to a predefined and configurable mapping strategy into a xe2x80x9cphysical addressxe2x80x9d that was placed on the memory bus to access a corresponding memory location. Hence, virtual memory management solved the problem of one-to-one correspondence.
Virtual memory management techniques continue to provide benefits today that enable the operating system of a computing system to effectively control where application programs are loaded and executed from memory in addition to providing a means whereby memory can be assigned to a program while it is running and then released back into the memory pool when the memory is no longer necessary. Most virtual memory management units today divide a system""s virtual memory into equal-sized chunks called memory pages. To access a memory page requires translation of the upper bits of a virtual address; the lower bits of the virtual address are not translated and merely represent an offset into a page.
Virtual memory management not only applies to the locations associated with memory, but also to the properties, or attributes, associated with those locations. For instance, a virtual page may be designated for reads only so that data writes to locations in the page can be precluded.
The virtual-to-physical address mapping information, along with information specifying the attributes of virtual memory pages, are stored in a designated area of memory known as a page table. Generally speaking, a page table contains one entry for each virtual memory page within the address space of a CPU. Hence, for each memory access, it is required that the page table entry associated with the access be retrieved so that the virtual address can be translated into a physical address and so that access attributes can be determined.
Translation lookaside buffers (TLBs) were incorporated into CPU designs for the express purpose of storing frequently used page table entries within a CPU so that memory accesses are not required each time an address is generated. A TLB is a very fast memory providing storage for a number of page table entries. TLBs are designed to be efficient and fast because they typically lie in the critical timing path of a CPU. Accordingly, only those information bits that are essential to the translation of addresses and specification of memory page attributes are provided in a page table entry within a TLB.
TLBs are streamlined to support rapid access for the translation of addresses. As a result, however, the structure of a given TLB is quite static, yielding little or no room for expansion. Hence, if it is desired to update the design of a CPU to incorporate a newly developed or expanded set of memory properties, then it is highly probable that the design of the CPU""s TLB must be modified to provide for expression of the properties at the virtual page level. But for CPU""s that have relegated TLB management tasks to operating system software, changing the structure of an existing TLB creates incompatibilities with the operating system softwarexe2x80x94the operating system must be updated in order to provide for memory management according to the new/expanded memory properties.
A significant market segment is lost, however, when an upgraded CPU becomes no longer compatible with an older operating system and its application programs. CPU manufacturers desire, at least, that CPU upgrades retain compatibility with older software. But compatibility retention in the case of a software-managed TLB architecture implies that the number of virtual memory attributes that are provided in a upgraded design be limited by the existing TLB structure. In other words, to retain compatibility with an older operating system means that little or no virtual page management features can be implemented in an upgraded CPU design.
Therefore, what is needed is an apparatus that allows expanded memory attributes to be provided via an existing TLB design, where the number of attributes exceeds the structure of the TLB, and where the structure of the TLB is maintained for compatibility with legacy software.
In addition, what is needed is a mechanism for extending the properties of virtual memory pages that utilizes an existing TLB structure.
Furthermore, what is needed is a CPU apparatus that allows more virtual memory page properties to be exercised than what an existing TLB structure accommodates, where the TLB structure also is backwards compatible with older operating system software.
Moreover, what is needed is a method for extending virtual memory page properties beyond the capacity of an existing TLB, but which defaults to states that can be interpreted by legacy applications software.
The present invention provides a superior technique for extending the properties of virtual memory pages beyond that provided for by an existing translation lookaside buffer (TLB). The properties of the virtual memory pages are extended according to the present invention without any detrimental impact on the structure of the TLB or any of the entries therein. The property extensions are provided for by the present invention in such a manner as to allow backwards compatibility with TLB management software in legacy operating systems.
In one embodiment, an apparatus is provided for specifying extended properties for virtual memory pages. The apparatus has a translation lookaside buffer (TLB) and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries, each of the plurality of TLB entries having an extended memory attributes index field, where the extended memory attributes index field prescribes legacy properties according to a legacy memory management protocol, and where the legacy properties comprise legacy cache management policies. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to said TLB, where the extended memory attributes index field designates the one of the plurality of extended memory attributes registers, and where contents of the one of the plurality of extended memory attributes registers prescribe specific extended properties for a corresponding virtual memory page. The plurality of extended memory attributes registers have initialization states that correspond to the legacy properties. The one of the plurality of extended memory attributes registers indicates an initialization legacy property that corresponds to the extended memory attributes index field.
One aspect of the present invention features a mechanism in a microprocessor for enabling a translation lookaside buffer (TLB) to extend the properties of virtual memory pages. The mechanism has an extended properties register array, for specifying a plurality of extended virtual page properties, and a memory management unit that is coupled to the extended properties register array. The memory management unit accesses the virtual memory pages. The memory management unit includes TLB entries and extended attributes logic. The TLB entries prescribe the properties of the virtual memory pages, where an extended memory attributes field within each of the TLB entries designates a corresponding register within the extended properties register array, and where the extended memory attributes field specifies legacy virtual page properties according to memory management rules employed by a legacy operating system. The extended attributes logic is coupled to the TLB entries. The extended attributes logic accesses the corresponding register to determine one of the plurality of extended virtual page properties that applies for accesses to a particular virtual memory page. The corresponding register is initialized to indicate specific legacy virtual page properties that correspond to contents of the extended memory attributes field according to the memory management rules.
Another aspect of the present invention contemplates a computer program product for use with a computing device. The computer program product has a computer usable medium, with computer readable program code embodied in the medium, for causing a CPU to be described, the CPU being capable of accessing virtual memory pages according to extended page properties. The computer readable program code includes first program code, second program code, and third program code. The first program code describes a translation lookaside buffer (TLB), where the TLB is configured to store TLB entries, each of the TLB entries having an extended page properties field, where the extended page properties field, according to a legacy operating system memory management protocol, prescribes page properties. The second program code describes extended attributes logic, where the extended attributes logic is configured to employ the extended page properties field to access an extended attribute register that is external to the TLB, and where contents of the extended attribute register determine the extended page properties for a particular virtual memory page, and where the extended attribute register is one of a plurality of extended attribute registers, and where the plurality of extended attribute registers is initialized to prescribe the legacy memory attributes according to the extended page properties field. The third program code describes a configuration register, wherein contents of the configuration register indicate whether or not the CPU is capable of providing the extended page properties.
Yet another aspect of the present invention provides a computer data signal embodied in a transmission medium. The computer data signal has first computer-readable program code, second computer-readable program code, third computer-readable program code, and fourth computer-readable program code. The first computer-readable program code describes a translation lookaside buffer (TLB), where the TLB is configured to store TLB entries, each having an extended page properties field. The second computer-readable program code describes extended memory attributes registers external to the TLB, where each of the extended memory attributes registers prescribes a set of extended attributes for accesses to virtual memory pages. The third computer-readable program code describes extended attributes logic, where the extended attributes logic is configured to employ the extended page properties field to access one of the extended memory attributes registers to determine a specific set of extended attributes whereby a specific virtual memory page is accessed, where the extended page properties field specifies legacy attributes for access to the virtual memory pages according to a legacy memory management protocol. The fourth computer-readable program code describes a configuration register, where contents of the configuration register indicate to an operating system that extended attributes features are available for use. The extended memory attributes registers are initialized to indicate the legacy attributes according to the legacy memory management protocol, and the one of the extended memory attributes registers is initialized to indicate particular legacy attributes corresponding to contents of the extended page properties field.
A further aspect of the present invention contemplates a method in a microprocessor for extending the properties of virtual memory pages over that provided for by existing translation lookaside buffer (TLB) entries. The method includes designating an existing field within each of the entries as an extended properties register index field and providing an array of extended properties registers external to the TLB that are indexed by the extended properties register index field; employing contents of the extended properties register index field to access a particular extended properties register within the array to extend the properties of a particular virtual memory page; initializing the array of extended properties registers so that they prescribe legacy properties as prescribed by contents of the extended properties register index field according to a legacy memory management protocol; and providing a configuration register in the microprocessor to indicate to an operating system that extended virtual page management features are available for employment. The employing includes first prescribing, within a first field of the particular extended properties register, an extended cache control policy for accesses to the particular virtual memory page; and second prescribing, within a second field of the particular extended properties register, an Instruction Set Architecture to be used for accesses to the particular virtual memory page.